![]() ![]() ![]() Wire PC_en // Computer enable signals wire PL_en // Player enable signals wire illegal_move // disable writing when an illegal move is detected //wire pos1,pos2,pos3,pos4,pos5,pos6,pos7,pos8,pos9 // positions stored wire win // win signal wire computer_play // computer enabling signal wire player_play // player enabling signal wire no_space // no space signal // position registers LED display for positions // 01: Player // 10: Computer output wirewho positions to play output wire pos1,pos2,pos3, Input clock, // clock of the game input reset, // reset button to reset the game input play, // play button to enable player to play input pc, // pc button to enable computer to play input computer_position,player_position, : FPGA projects, Verilog projects, VHDL projects // Verilog code for TIC TAC TOE GAME // Top level module module tic_tac_toe_game( ![]()
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